Central Processing Unit (CPU)#
- Instruction Fetch (IF): increase PC
- Instruction Decode (ID): read OP and register
- Execution (EX): ALU executes command
- Memory Stage (M): read/write to memory
- Write Back (WB): load from memory to register?
Hazards are problems due to pipelining.
- Structural Hazard: same resource is needed multiple times in the same cycle.
- Data Hazard: data dependencies (read-after write, write-after-write, write-after-read).
- Control Hazard: next executed instruction is not the next specified instruction due to jump, branch, exception.